Switched-capacitor circuits have widespread use due to the advancement of CMOS technology. CMOS technology is commonly used to implement switched-capacitor circuits because of the availability of MOSFET switches and op amps with low input bias currents. One common type of switched-capacitor circuit is a switched-capacitor integrator. CMOS switched-capacitor integrator circuits are commonly used in sigma delta analog-to-digital converters. Such CMOS switched-capacitor integrator circuits typically include switches, capacitors and op amps.
CMOS technology produces switches and capacitors with high performance and yield. CMOS op amps, however, suffer from a number of drawbacks. Particularly, CMOS op amps typically have input offset voltages within the range of 1-10 mv (whereas ideally the input offset voltage should be zero). During operation, the difference between the voltages on the input terminals of the op amp will be equal to the input offset voltage, when the output voltage is at zero volts. In addition, such op amps typically have a finite gain within the range of 100-1,000,000 (though ideally the gain should be infinite). As a result of the finite gain, there exists an additional error voltage between the op amp input terminals that varies as the output voltage varies, causing inaccurate performance. Therefore, CMOS op amps can significantly adversely affect the accuracy of the circuit in which they are used.
To compensate for the non-ideal performance of CMOS op amps, there exist a number of prior art switched-capacitor circuits with auto-zeroing features useful for reducing op amp offset voltage and gain errors. Among these prior art auto-zero circuits, the simpler circuits attempt to compensate for the input offset voltage and gain error voltage either by measuring the value of the offset voltage and gain error voltage while ignoring the output voltage completely or by measuring the value of the offset voltage while making assumptions about the final value of the output voltage based on the value of the output voltage during a proceeding clock phase. Such circuits operate inaccurately if the op amp gain is too low and/or the output voltage significantly varies between clock phases (which variation is common with certain switched capacitor circuits such as sigma-delta integrators). The more complex circuits, while operating more accurately, require additional circuitry for determining the final value of the output voltage.
FIG. 1 shows a prior art, switched-capacitor auto-zero integrator. This prior art circuit (the Nagaraj circuit) was introduced by K. Nagaraj in Magaraj, K., Vlach, J., Viswanathan, T. R. and Singhal, K., "Switched-Capacitor Integrator with Reduced Sensitivity to Finite Amplifier Gain," Electronics Letters, Vol. 22, 1986, pp. 1102-1105, which is herein incorporated by reference. The Nagaraj circuit aims to reduce op amp offset voltage and gain errors by measuring the offset voltage and gain error voltage and thereafter compensating for them.
The Nagaraj circuit includes an input line 10 and an op amp 12. The op amp has an inverting input line 16 a non-inverting input line 18 and an output line 14. Also included are an input capacitor C.sub.1 connected between input node N1 and summing node N3, an integrating capacitor C.sub.2 connected between integration-node N2 and the output line 14, and an offset capacitor C.sub.3, connected between summing node N3 and the inverting input line 16.
The circuit also includes three switches (S1, S2 and S3) operable (i.e., closed) when control signal .PHI.1 is high, and two switches S4 and S5 operable when a control signal .PHI.2 high. Switch S1 is connected between input node N1 and ground, switch S2 is connected between summing node N3 and ground, and switch S3 is connected between the inverting input line 16 and integration node N2. Switch S4 is connected between the input line 10 and input node N1 and switch S5 is connected between summing node N3 and integration node N2.
Shown in the timing diagram of FIG. 4 are the control signals .PHI.1 and .PHI.2 which respectively control the operation of the .PHI.1 switch set (S1, S2 and S3) and the .PHI.2 switch set (S4 and S5). (Signals .PHI.1 and .PHI.2 are shown on the same time axis and the vertical placement of one above the other does not signify that one attains different voltage levels than the other; the "high" and "low" voltage levels of the signals are relative to each other only). As is conventional for a switched-capacitor integrator, the .PHI.1 and .PHI.2 switch sets of the Nagaraj circuit operate in two non-overlapping time intervals (or clock phases). During interval 1, signal .PHI.1 is at a "high" voltage level and signal .PHI.2 is at a "low" voltage level. During interval 2, signal .PHI.1 is low and signal .PHI.2 is high. Signal .PHI.1 controls the .PHI.1 switch set (S1, S2 and S3) such that, during interval 1 (when .PHI.1 is high), switches S1, S2 and S3 are closed and during interval 2 (when .PHI.1 is low), switches S1, S2 and S3 are opened. Conversely, because the .PHI.2 switch set (S4 and S5) is controlled by control signal .PHI.2, switches S4 and S5 are open during interval 1 and are closed during interval 2. It is important that the signals .PHI.1 and .PHI.2 are not high at the same time so that the input voltage is not lost through switches S4 and S1 to ground. Thus as will be understood by those skilled in the art the circuit typically applies a "break-before-make" operation to ensure that the control signals are not simultaneously high.
During interval 1, the input capacitor C.sub.1 is connected to ground through switches S1 and S2. This arrangement resets the input capacitor C.sub.1 to zero charge (and voltage). During the interval 2, switches S1, S2 and S3 are opened and switches S4 and S5 are closed. The input capacitor C.sub.1 is charged to the input voltage V.sub.in (received through input line 10) through switch S4, and the integrating capacitor C.sub.2 is (ideally) charged to the same charge to compensate for the charge on the input capacitor C.sub.1. As will be understood by those skilled in the art, because C.sub.3 holds a voltage equal and opposite to the op amp input offset and gain error voltages there is essentially an equipotential surface between the right plate of capacitor C.sub.1 and left plate of capacitor C.sub.2, C.sub.3 being treatable as an open circuit. The combined charge on the right plate of C.sub.1 and left plate C.sub.2 is shared. (By conservation of charge, of course, the total "charge" on C.sub.1, and C.sub.2 is unchanged from interval 1 to interval 2). Thus, during interval 2 when the input capacitor C.sub.1 is charged by the input voltage V.sub.in, the output of the op amp moves to a voltage to charge capacitor C.sub.2 and compensate for the charge build-up on capacitor C.sub.1. The charging of capacitor C.sub.2 to compensate for the charge on capacitor C.sub.1 is herein referred to as charge "compensation".
The Nagaraj circuit measures the offset voltage and gain error voltage during interval 1 by charging offset capacitor C.sub.3 with the offset voltage and gain error voltage of the op amp. By holding this charge on capacitor C.sub.3 during integration (interval 2), the circuit attempts to correct for the offset and gain error voltages. The theory is that the voltage on summing node N3 will be reduced, due to the charge held on capacitor C.sub.3, which enables accurate integration of the input voltage (while belong insensitive to op amp offset and gain error voltages). The offset voltage and gain error voltage, however, are measured during interval 1 with the output voltage possibly not at its final value (i.e., the value at the end of interval 2). Therefore, if the output voltage changes between interval 1 and interval 2, and thus the gain error voltage changes appreciably between the time intervals, the above-stated simplifications no longer hold true and the Nagaraj circuit will operate inaccurately.
Particularly, during interval 1, while input capacitor C.sub.1 is grounded, offset Capacitor C.sub.3 will charge up to the voltage: V.sub.3 =V.sub.OS -V.sub.o1 /A, where V.sub.OS is the offset voltage, V.sub.o1 is the op amp Output voltage at the end of interval 1 and A is the op amp gain. At the same time, input capacitor C.sub.1 will be discharged. During interval 2, C.sub.1 will be charged by the input voltage V.sub.in, which charge will cause the integrating capacitor C.sub.2 to be charged and the value of the output voltage on output line 14 will change such that the Voltage V.sub.- at the op amp inverting input line 16 will be equal to: V.sub.- =V.sub.OS -V.sub.o2 /A, where V.sub.02 is the op amp output voltage at the end of interval 2. The voltage on summing node N3 will be equal to V.sub.S =V.sub.- -V.sub.3 =(V.sub.o1 -V.sub.02)/A.
Ideally, the voltage v.sub.S at summing node N3 should be equal to zero to ensure perfect charge compensation of integrating capacitor C.sub.2 due to the charging of input capacitor C.sub.1. In the case where the amplifier gain A is very large for example 10.sup.6, the summing node voltage V.sub.S, will be negligible. However, in the case where the amplifier gain A is lower, for example 102 the summing node voltage voltages V.sub.01 and V.sub.02, the voltages are so close in value as to produce a small summing node voltage V.sub.S even with a low amplifier gain A. However, in the case of certain CMOS circuits such as sigma-delta modulators, the op amp output changes value significantly from time interval to time interval and, therefore, there exists errors due to finite amplifier gain.
FIG. 2 shows another prior art auto-zero integrator (the Larson circuit) which was introduced by Larson in Larson, L. E., and Temes, G. C. "Switched-Capacitor Building-Blocks with Reduced Sensitivity to Finite Amplifier Gain, Bandwidth, and Offset Voltage," International Symposium on Circuits and Systems, 1987, pp. 334-338, which is herein incorporated by reference. The Larson circuit is an improvement over the Nagaraj circuit and measures the offset and gain error voltages based on an estimate of the value of the output voltage at the end of interval 2. The Larson circuit assumes, however, that the input voltage V.sub.in remains at the same level during both interval 1 and interval 2. If the input voltage changes between interval 1 and interval 2 (causing the output voltage to change), the Larson circuit will operate inaccurately.
As shown in FIG. 2, the Larson circuit includes two additional capacitors to those of the Nagaraj circuit (like elements are referred to by same reference characters to those in FIG. 1). The extra capacitors C.sub.4 and C.sub.5 are topologically arranged in parallel with the input capacitor C.sub.1 and the integrating capacitor C.sub.2, respectively but being controlled by different switches are never physically connected in parallel. In the Larson circuit, the value of C.sub.4 equals twice the value of C.sub.1 and the value of C.sub.5 equals C.sub.2. The timing diagram of the control signals .PHI.1 and .PHI.2 is shown in FIG. 4 and is identical to that of the Nagaraj circuit. Switches S1, S2 and S6 are controlled by signal .PHI.1 and switches S4, S5, S7 and S8 are controlled by signal .PHI.2.
During interval 1, capacitor C.sub.5 serves as the integration capacitor and node N4 acts as the summing node. The output moves to a voltage that anticipates the interval 2 output voltage. The left plate of the input capacitor C.sub.1 is connected through switch S1 to ground and the right place of input capacitor C.sub.1 is connected through switch S2 to node N4 between capacitors C.sub.4 and C.sub.5. Input capacitor C.sub.1 is charged by the offset voltage and gain error voltage of the op amp 12 corresponding to an approximate final output voltage value, assuming the input voltage V.sub.in remains at the same level between interval 1 and interval 2. During interval 2, capacitor C.sub.1 is further charged by the input voltage V.sub.in and the voltage V.sub.S at the summing node N3 will charge to the op amp offset voltage and gain error voltage corresponding to the final value (at the end of interval 2) of the output voltage. If the input voltage V.sub.in has not changed between intervals, the voltage V.sub.S will be approximately the same as the voltage on node N4 during interval 1. Consequently, the only charge compensation of integrating capacitor C.sub.2 will be due to the charging by input voltage V.sub.in of input capacitor C.sub.1. In other words, the circuit is insensitive to op amp offset voltage and finite gain.
Not only does the Larson circuit require extra capacitors than does the Nagaraj circuit, but also if the input voltage V.sub.in changes value between interval 1 and interval 2, the Larson circuit operates inaccurately.
FIG. 3 shows an even further prior art auto-zero switched-capacitor integrator (the Hurst circuit). The Hurst circuit was introduced by Hurst in Hurst P. J., and Levinson, R. A., "Delta-Sigma A/Ds with Reduced Sensitivity to Op Amp Noise and Gain," International Symposium on Circuits and Systems, 1989, pp. 254-257, which is herein incorporated by reference. FIG. 3 includes identical reference characters to denote like elements to those of FIGS. N1 and 2N The timing diagram of switch control signals .PHI.1 and .PHI.2 is shown in FIG. 4.
Essentially, in the Hurst circuit, the capacitor C.sub.4 in the Larson circuit is split into two capacitors C.sub.11 and C.sub.6 both with value C.sub.1. The input voltages V.sub.in (n) and V.sub.in (n-0.5) are sampled versions of the same voltage at different times. Capacitor C.sub.11 samples the input voltage V.sub.in as C.sub.4 did in the Larson circuit and capacitor C.sub.6 samples a half-cycle delayed version V.sub.in (n-0.5) of the input voltage. Assuming the input voltage V.sub.in (n) changes during interval 1, the function of capacitor C.sub.6 during interval 1 is to cancel the charge on capacitor C.sub.1. Therefore, only the charge from capacitor C.sub.11 will be integrated by capacitor C.sub.5. If the input voltage V.sub.in (n) does not change from interval 1 to interval 2, the charge on the right hand plate of capacitor C.sub.1 is the same as that during interval 1 and, thus, the only charge compensation occurring between C.sub.1 and C.sub.2 is due to the input voltage V.sub. in.
While the Hurst circuit is relatively insensitive to finite op amp gain, the circuit includes three additional capacitors and associated switches (to those of an uncompensated circuit), which increase the manufacturing cost and consume additional area on an integrated circuit chip.
Accordingly, a general object of the present invention is to provide a switched capacitor integrator with an auto-zeroing capability for accurately reducing offset voltage and gain errors which otherwise would be introduced by the op amp and which integrator will be relatively simple and inexpensive to implement.